GSoC 2023 (Week 5 and 6): Incorporating sequential and internal combinational delays

Introduction

You can find my previous blog here. I completed the DSP48E1 primitive. Now one can successfully generate bitstreams for designs containing DSP blocks. For now, only structural instantiation is possible for DSP slices. I will be working on the behavioural instantiation as a part of my stretch goals for this project after I am done with all other deliverables. In this blog, I discuss updating DSP48E1 primitive with timing values.

Timing database

The Project X-Ray database contains timing information for each tile type. The setup and hold times of a tile vary according to its configuration. The database has setup and hold times for each combination of features. A part of the database for the DSP slice is shown below(setup and hold times of the D input). Each of the cell types in the database is different from each other and represent a DSP slice in that particular configuration.

(CELL
        (CELLTYPE "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_NO_PATDET")
        (INSTANCE DSP48E1)
        (TIMINGCHECK
            (HOLD D (posedge CLK) (-4.951::-0.994))
            (SETUP D (posedge CLK) (0.994::4.951))
        )
    )
(CELL
        (CELLTYPE "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_DYNAMIC_USE_PATTERN_DETECT_PATDET")
        (INSTANCE DSP48E1)
        (TIMINGCHECK
            (HOLD D (posedge CLK) (-5.342::-1.063))
            (SETUP D (posedge CLK) (1.063::5.342))
        )
(CELL
        (CELLTYPE "DSP48E1_ADREG_0_DREG_0_MREG_0_PREG_1_USE_DPORT_TRUE_USE_MULT_MULTIPLY_USE_PATTERN_DETECT_PATDET")
        (INSTANCE DSP48E1)
        (TIMINGCHECK
            (HOLD D (posedge CLK) (-5.342::-1.063))
            (SETUP D (posedge CLK) (1.063::5.342))
        )
    )
(CELL
        (CELLTYPE "DSP48E1_ADREG_0_DREG_0_MREG_1_USE_DPORT_TRUE_USE_MULT_DYNAMIC")
        (INSTANCE DSP48E1)
        (TIMINGCHECK
            (HOLD D (posedge CLK) (-3.158::-0.249))
            (SETUP D (posedge CLK) (0.249::3.158))
        )
    )

Updating DSP48E1 primitive with timing information

All the primitives have placeholders in place of setup and hold times of inputs and outputs. While generating the routing graph, a Python script (update_arch_timings.py) injects values to these placeholders from the timing database using a handcrafted JSON file(bels.json). The JSON file helps in mapping the correct timing values for each mode in the DSP48E1 primitive hierarchy.

I updated the DSP primitive with placeholder values for setup and hold times of all I/O pins. Apart from these, internal combinational delays also need to be considered. These internal delays will be different depending on the number of pipelining registers used for each mode. The JSON file mentioned above needs to be updated as well. For more information regarding the time modelling of primitives, see VTR docs.

Adding DRC to the VPR libraries

To prevent entering illegal values of instantiation parameters, I have included a few design rule checks in the cells_map.v. DSP48E1 user guide needs to be followed for this purpose. A portion of the DRC is shown below:

case (A_INPUT)
             "DIRECT", "CASCADE" : ;
              default : begin
                       $error("A_INPUT on DSP48E1 instance is set to an illegal value. Valid options for this parameter are DIRECT or CASCADE");
                        end
endcase
case (B_INPUT)
             "DIRECT", "CASCADE" : ;
              default : begin
                       $error("B_INPUT on DSP48E1 instance is set to an illegal value.  Valid options for this parameter are DIRECT or CASCADE");
                  end
endcase
case (AREG)
            0, 1, 2 : ;
            default : begin
                    $error("AREG on DSP48E1 instance is set to an illegal value. Valid options for this parameter are 0, 1 or 2");
                  end
endcase
case (AREG)
            0 : if(AREG != ACASCREG) begin
                    $error("ACASCREG  on DSP48E1 instance is set to an illegal value.  ACASCREG has to be set to 0 when AREG is 0");
                    end
            1 : if(AREG != ACASCREG) begin
                    $error("ACASCREG  on DSP48E1 instance is set to an illegal value.  ACASCREG has to be set to 1 when AREG is 1");
                    end
            2 : if((AREG != ACASCREG) && ((AREG-1) != ACASCREG)) begin
                    $error("ACASCREG  on DSP48E1 instance is set to an illegal value. ACASCREG has to be set to either 2 or 1 when AREG is 2");
                    end
            default : ;
endcase

Achievements

1. Added sequential timings in the DSP48E1 primitive.

2. Added internal combinational delay timings in the DSP48E1 primitive.

3. Added Design Rules Check in the VPR libraries

All the changes can be found in this pull request.

Blockers

1. Some timing values were absent from the project X-Ray database. I had to include some fake timing values to make it work.

Targets for the next week

1. Add support for DSP48E1 to fasm2bels which will allow decoding of F4PGA-generated bitstreams to bels which can then be processed via Vivado to produce a bitstream. These two sets of bitstreams can then be cross-checked for errors.

2. Add multiple modes to the DSP48E1 primitive that differ considerably in timing characteristics.