Computer Architecture

John Von Neumann Architecture

• He is considered one of the greatest mathematicians and computer scientists of the 1900s who came up with an innovative, simple, elegant architecture of what a computer is. It is often referred to as 'Stored Program Concept'.

• The Stored program concept means a program is executed on the CPU while it is residing inside the RAM.

Q. What is a program?

A program is a sequence of instructions. This usually exists in a machine-level language.

Basic CPU Architecture

Whenever a human writes a program in any language (for instance "C Language"). After its compilation, it converts the all instructions of the program into Machine-level instructions that only the machine can understand and these instructions are stored inside the RAM and ready to be executed on CPU.

Instruction Cycles

The instruction cycle (also known as the fetch–decode–execute cycle, or simply the fetch-execute cycle) is the cycle that the central processing unit (CPU) follows from boot-up until the computer has shut down in order to process instructions. It is composed of three main stages: the fetch stage, the decode stage, and the execute stage.

This is also known as fetch-decode-execute cycle.

As shown in the above figure, let's dive into each of the components residing in the registers.

1. Fetch Stage: This is the initial stage of the cycle, where the CPU retrieves the next instruction to be executed. It involves the following steps:

   • The program counter (PC) holds the memory address of the next instruction.

   • The PC's value is copied into the memory address register (MAR), pointing to the instruction's location in memory.

   • The instruction is fetched from memory and stored in the memory data register (MDR), which can act as a buffer.

   • Finally, the instruction is copied into the current instruction register (CIR), where it waits for further processing.

2. Decode Stage: In this stage, the CPU deciphers the fetched instruction to determine what operation it should perform and which operands it should use. This stage prepares the CPU for the execution of the instruction.

3. Execute Stage: During this stage, the CPU carries out the actual instruction. The control unit sends control signals to the relevant functional units of the CPU. This can involve actions like reading data from registers, performing arithmetic or logical operations in the arithmetic logic unit (ALU), and storing results back in registers or memory. The program counter may also be updated to point to the next instruction. The ALU performs arithmetic operations such as addition and subtraction and also multiplication via repeated addition and division via repeated subtraction. It also performs logic operations such as AND, OR, NOT, and binary shifts as well. The FPU is reserved for performing floating-point operations.

Interrupts

The moment when something halts the flow

Interrupts are events that can "interrupt" the normal flow of a program or CPU execution. They occur asynchronously and can be triggered by various sources, including hardware events (e.g., keyboard input) or software events (e.g., system calls). When an interrupt occurs, the CPU temporarily suspends its current task to handle the interrupting event. Once the interrupt is handled, the CPU can then resume its previous task.

For example, consider the case of reading user input with input() during program execution. When the input() function is encountered, it might pause the program and wait for the user to provide input, effectively interrupting the program's flow. Once the user provides input, the program can resume its execution.

Similarly, in the case of output, if multiple tasks or processes are trying to print to a shared output device (e.g., a display or a printer), an interrupt mechanism can be used to manage and prioritize these requests. The interrupt system ensures that each task gets its turn to output information without causing delays or conflicts.

In summary, interrupts are a vital part of modern computing systems, allowing for efficient handling of external events and ensuring that the CPU can manage multiple tasks or events concurrently. When an interrupt occurs, it temporarily diverts the CPU's attention to address the interrupting event before returning to its regular execution flow.