Some Common Computer Architecture Terms

1. Single Cycle Datapath

A single cycle datapath executes every instruction in one clock cycle. This means that all stages of instruction processing (fetch, decode, execute, memory access, and write-back) are completed in one cycle.

• Example: A basic RISC (Reduced Instruction Set Computer) processor where each instruction is completed in one clock cycle. For instance, if an ADD instruction is executed, the instruction fetch, decode, register read, ALU operation, memory read/write, and register write-back all occur within a single clock cycle.

• Pros: Simplicity in design and control.

• Cons: The clock cycle time must be long enough to accommodate the longest instruction, making it inefficient for complex instructions.

2. Multi-Cycle Datapath

A multi-cycle datapath breaks down the instruction execution into multiple cycles. Each instruction is executed in steps, with each step taking a separate clock cycle. This allows the processor to use the same hardware for different parts of the instruction cycle, depending on the phase of execution.

• Example: A MIPS processor that breaks down instruction execution into different cycles: one for instruction fetch, one for instruction decode and register fetch, one for ALU operations, one for memory access (if needed), and one for register write-back.

• Pros: More efficient use of hardware, shorter clock cycles compared to a single-cycle datapath.

• Cons: More complex control logic is required to handle different instruction phases.

3. Pipelined Datapath

Pipelining is a technique where multiple instructions are overlapped in execution. The instruction processing is divided into several stages, with each stage performing a part of the instruction cycle (fetch, decode, execute, etc.). Each stage processes a different instruction simultaneously, improving throughput.

• Example: A classic 5-stage pipeline in RISC processors includes stages like Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write-Back (WB). While the first instruction is in the EX stage, the second can be in the ID stage, and the third in the IF stage.

• Pros: Increases instruction throughput.

• Cons: Pipeline hazards (data hazards, control hazards) can stall the pipeline, requiring sophisticated hazard detection and control mechanisms.

4. Out-of-Order Execution

Out-of-order execution allows instructions to be processed as resources are available rather than strictly in the order they appear in the program. This approach aims to maximize the utilization of the CPU by dynamically scheduling instructions to avoid stalls.

• Example: Modern x86 processors, such as Intel’s Core series, which use dynamic scheduling (Tomasulo's algorithm) to issue instructions out of order but retire them in order to maintain correct program execution.

• Pros: Improved performance by avoiding pipeline stalls.

• Cons: Complexity in managing dependencies and maintaining program order.

5. Superscalar Architecture

A superscalar processor can issue and execute more than one instruction per clock cycle. It relies on multiple execution units (such as ALUs, FPUs) to achieve parallel instruction execution.

• Example: The Intel Core i7 processor, which can issue multiple instructions per cycle across multiple execution units.

• Pros: Higher throughput and performance due to parallel execution.

• Cons: Requires complex instruction scheduling and resource management.

6. Speculative Execution

Speculative execution allows a processor to execute instructions before it is certain that they are needed, based on a prediction (like branch prediction). If the speculation is correct, the results are used; if not, they are discarded, and execution resumes from the correct point.

• Example: Modern processors (e.g., ARM Cortex-A series) use branch predictors to speculate the path of conditional branches and execute instructions speculatively.

• Pros: Increases instruction throughput by minimizing stalls.

• Cons: If the speculation is incorrect, it leads to wasted cycles and potential security vulnerabilities (e.g., Spectre).

7. VLIW (Very Long Instruction Word)

VLIW processors issue multiple operations encoded in a single long instruction word. The compiler is responsible for determining which operations can be executed in parallel and encoding them into VLIW instructions.

• Example: The Itanium processor by Intel, which relies on the compiler to determine instruction parallelism.

• Pros: Simplifies hardware by shifting scheduling complexity to the compiler.

• Cons: Dependence on compiler sophistication; not efficient for dynamic workloads.

8. Flynn's Taxonomy

Flynn's taxonomy classifies computer architectures based on the number of concurrent instruction (I) and data (D) streams they support:

• SISD (Single Instruction, Single Data): A traditional uniprocessor system where one instruction operates on one data stream at a time.

  • Example: A standard sequential processor like an early Intel 8086 CPU.

• SIMD (Single Instruction, Multiple Data): Executes the same instruction on multiple data streams simultaneously.

  • Example: Graphics Processing Units (GPUs), which perform the same operation on many pixels in parallel.

• MISD (Multiple Instruction, Single Data): Multiple instructions operate on a single data stream. Rare and often theoretical.

  • Example: Fault-tolerant computers that perform the same operations differently to detect and correct errors.

• MIMD (Multiple Instruction, Multiple Data): Multiple autonomous processors execute different instructions on different data.

  • Example: Multi-core processors like AMD Ryzen or Intel Xeon, where each core can execute different instructions on different data independently.

Summary of Flynn's Taxonomy Classes with Examples:

1. SISD: Early Intel 8086 processor.

2. SIMD: GPUs, Intel AVX (Advanced Vector Extensions) in CPUs.

3. MISD: Theoretical; rarely implemented in practice.

4. MIMD: Modern multi-core processors (e.g., Intel Xeon, AMD Ryzen).

9. RISC (Reduced Instruction Set Computer)

RISC is a type of processor architecture that utilizes a small, highly optimized set of instructions. The philosophy behind RISC is to keep the instruction set simple and execute instructions quickly. Each instruction is designed to perform a single, simple operation, and all instructions typically take the same amount of time to execute.

• Example: ARM processors, widely used in mobile devices and embedded systems, and the MIPS architecture are examples of RISC processors. Another notable example is the RISC-V architecture, which is gaining popularity due to its open-source nature.

• Advantages:

  • Simplicity: The simpler instruction set makes it easier to design and optimize the pipeline.

  • Speed: Each instruction can typically be executed in one clock cycle, improving throughput.

  • Power Efficiency: Reduced instruction complexity often leads to lower power consumption, which is ideal for mobile and embedded systems.

  • Easier to Optimize with Compilers: The regularity of instructions makes it easier for compilers to optimize code.

• Disadvantages:

  • Code Size: Because RISC processors use simpler instructions, more instructions may be needed to perform a complex task, potentially increasing code size.

  • Dependency on Compiler Quality: RISC architecture's performance is highly dependent on the compiler's ability to efficiently optimize code.

10. CISC (Complex Instruction Set Computer)

CISC is a processor architecture that uses a broader set of instructions, with each instruction capable of performing multi-step operations or addressing modes. The philosophy behind CISC is to reduce the number of instructions per program, ignoring the complexity of each instruction.

• Example: The x86 architecture used in most desktop and laptop computers is a prime example of a CISC design. The IBM System/360, one of the earliest computers to implement a CISC architecture, also falls into this category.

• Advantages:

  • Compact Code: Fewer instructions are needed to perform complex tasks, which can reduce the size of the program.

  • Compatibility and Versatility: CISC processors can support a wide variety of high-level programming constructs directly with fewer machine instructions, making them versatile.

  • Efficient Memory Usage: Fewer instructions and addressing modes can reduce the need for multiple memory accesses.

• Disadvantages:

  • Complexity in Design: The complexity of the instruction set increases the complexity of the hardware, making it harder to optimize.

  • Power Consumption: More complex instructions can lead to higher power consumption and heat dissipation.

  • Variable Instruction Lengths: The use of instructions of varying lengths can complicate the design of pipelines and caching strategies.

Comparison of RISC and CISC with Examples

The 7 dimensions of an Instruction Set Architecture (ISA) are key characteristics that define how a processor interacts with software and hardware. These dimensions help in understanding the design and functionality of a processor's instruction set. Here are the 7 dimensions:

1. Operand Storage in the CPU

This dimension describes where the operands (data) for the instructions are stored in the CPU. It can vary based on the architecture:

• Accumulator-Based: Uses a single accumulator register where one operand is stored, and the other comes from memory.

• Stack-Based: Operands are stored on a last-in, first-out (LIFO) stack in memory.

• Register-Based: Uses a set of registers for operands. Most modern processors are register-based, meaning they use multiple general-purpose registers to hold operands.

2. Number of Explicit Operands per Instruction

This dimension defines how many operands are explicitly mentioned in an instruction. Different architectures have different approaches:

• Zero Address (Stack-Based): Instructions operate implicitly on the top of the stack.

• One Address: Instructions have one explicit operand, often with the other operand implicit (like the accumulator).

• Two Address: Instructions specify two explicit operands (e.g., ADD R1, R2).

• Three Address: Instructions specify three explicit operands (e.g., ADD R1, R2, R3).

3. Operand Location

This dimension determines where the operands can reside (memory, registers, or both):

• Register-Only: Operands must be in registers.

• Memory-Register: One operand in memory and one in a register.

• Memory-Memory: Both operands can be in memory (rare in modern architectures due to inefficiency).

4. Operations Supported

This dimension refers to the types of operations the ISA supports. It includes:

• Data Movement: Operations like LOAD, STORE, MOVE.

• Arithmetic: Operations like ADD, SUBTRACT, MULTIPLY, DIVIDE.

• Logical: Operations like AND, OR, NOT, XOR.

• Control Transfer: Operations like JUMP, CALL, RETURN.

• Floating-Point: Operations for handling floating-point arithmetic.

5. Type and Size of Operands

This dimension specifies the types (integer, floating-point, character, etc.) and sizes (8-bit, 16-bit, 32-bit, 64-bit) of operands that the ISA can handle. The architecture must support operations for different operand types and sizes.

6. Instruction Format

This dimension refers to the layout of bits in an instruction, including:

• Length: Fixed-length (all instructions are the same size, as in RISC) or variable-length (instructions of different sizes, as in CISC).

• Field Positions: The location of operation code (opcode), source and destination operands, immediate values, etc.

• Encoding: The binary representation of instructions, affecting how compactly instructions can be represented and stored.

7. Addressing Modes

This dimension defines the methods used to specify the operands' addresses. Addressing modes determine how the effective address of the operand is computed. Common addressing modes include:

• Immediate: Operand value is part of the instruction.

• Direct: Address of the operand is given explicitly in the instruction.

• Indirect: Instruction specifies a register or memory location that holds the address of the operand.

• Register: Operand is located in a register.

• Indexed: Effective address is computed by adding a constant value to the contents of a register.

• Base + Offset: Combines base register with an offset to compute the effective address.

• PC-Relative: Address is computed relative to the Program Counter (useful for branch instructions).