How to send audio file in DE1-SoC FPGA?


Sending an audio file to the DE1-SoC FPGA involves a few key steps, depending on your exact use case (e.g. playback through audio codec, audio processing, or storage). Below is a comprehensive overview of how you can send and use audio data on the DE1-SoC development board, which includes both a Cyclone V FPGA and an ARM Cortex-A9 HPS (Hard Processor System).
🔧 Key Hardware Interfaces Involved
WM8731 Audio CODEC: The DE1-SoC includes a Wolfson WM8731 chip for audio input/output (microphone, line-in, line-out, headphone).
FPGA (Cyclone V): Can be used for custom DSP (Digital Signal Processing), data handling, or interfacing.
HPS (ARM Cortex-A9): Can load audio files from SD card, Ethernet, or USB and interact with the FPGA.
✅ Step-by-Step Guide
### 1. Prepare the Audio File
Format: Typically 16-bit PCM WAV is used.
Sampling rate: Match the codec's settings (e.g. 44.1 kHz or 48 kHz).
Mono or Stereo: Based on your codec setup.
Use Audacity
or a script (e.g. Python or MATLAB) to convert to raw PCM if needed.
### 2. Choose How You Send the Audio File
You can send the audio to the DE1-SoC in various ways:
✅ Option A: Using HPS Linux
Boot Linux (e.g. Angstrom or custom Linux) on HPS from SD card.
Copy audio file via:
SCP or FTP over Ethernet
USB drive
SD card mounted in Linux
Play Audio or Send to FPGA:
Use
aplay
or similar command to play through codec (handled by HPS).Or write a program in C to open the audio file, extract PCM data, and send it via memory-mapped I/O to the FPGA.
✅ Option B: From PC via UART/USB
Use a serial terminal (like PuTTY or Python script with
pyserial
) to send the file byte-by-byte over UART to HPS.HPS receives and stores or streams audio to FPGA.
⚠️ UART is slow (~115200 bps), so not good for real-time playback of high-quality audio.
✅ Option C: Use SD Card Directly
Store the file on SD card.
Read it in either HPS (Linux C program) or from FPGA using an SD card interface (more complex in HDL).
### 3. Send Data from HPS to FPGA
This can be done via AXI bridge (HPS ↔ FPGA):
Use lightweight HPS-to-FPGA bridge for memory-mapped control registers.
Use FPGA-to-HPS SDRAM or shared memory for bulk data transfer.
C code (HPS side):
c
volatile uint32_t *audio_fifo = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, HPS_TO_FPGA_BRIDGE_BASE);
// Write audio samples to audio_fifo[i]
### 4. FPGA Side – Audio Output
Implement or use provided IP for WM8731 interface (I²S).
FIFO buffer to store incoming samples.
Clocked I²S interface to feed the samples to the audio codec in sync.
HDL components:
FIFO
I²S Transmitter
Control FSM
Intel provides Audio and Video IP Cores, and Terasic provides example projects (DE1_SoC_Audio
).
📦 Example Project Resources
Terasic DE1-SoC CD: Includes
audio demonstration
code (Verilog/Quartus + HPS C-code)Intel University Program: Look for DE1-SoC audio labs
GitHub Repos: Search for
DE1-SoC audio streaming
orDE1-SoC i2s wm8731
✅ Tips
Always match bit depth and sample rate with codec settings.
Buffering is essential to avoid underruns.
Use DMA for efficient transfer from HPS memory to FPGA FIFO if needed.
Confirm correct clock settings (e.g. MCLK, BCLK for I²S).
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