Blinky LED project using open-source FPGA tools on the Lattice iCEStick board

ampheoampheo
2 min read

Now let’s do the blinky LED project using open-source FPGA tools on the Lattice iCEStick board. This is a great way to work fully license-free, using Verilog and powerful tools like Yosys, nextpnr, and iceprog.


Project: Blinking LED on Lattice iCEStick (iCE40HX1K)


What You Need

ItemDetails
FPGA BoardLattice iCEStick (iCE40HX1K-TQ144)
Software (Linux/macOS/WSL)Yosys, nextpnr, IceStorm tools (icestorm, iceprog)
LanguageVerilog
OSLinux / WSL (best), or macOS
ProgrammerBuilt into iCEStick (via USB)

Step-by-Step Tutorial


1. Install Tools

On Ubuntu/Debian/WSL:

bash

sudo apt install yosys nextpnr iceprog icestorm

Or follow the official install guide:


2. Write the Verilog Code

Create a file blinky.v:

verilog

module blinky (
    input clk,           // 12 MHz clock on iCEStick
    output LED
);

reg [23:0] counter = 0;

always @(posedge clk) begin
    counter <= counter + 1;
end

assign LED = counter[23];  // Blink frequency depends on this bit

endmodule

3. Write the PCF Constraints File

Create blinky.pcf to map logical pins to iCEStick physical pins:

pcf

set_io clk 21       # iCEStick 12 MHz clock
set_io LED 99       # iCEStick LED on pin 99 (usually LED1)

4. Synthesize & Build Bitstream

Run these steps in terminal:

bash

# Step 1: Synthesize Verilog
yosys -p "synth_ice40 -top blinky -json blinky.json" blinky.v

# Step 2: Place-and-route
nextpnr-ice40 --hx1k --package tq144 --pcf blinky.pcf --json blinky.json --asc blinky.asc

# Step 3: Generate bitstream
icepack blinky.asc blinky.bin

5. Program the iCEStick

Plug in the iCEStick and run:

bash

iceprog blinky.bin

The onboard LED should now blink!


What’s Going On?

  • counter counts up every 12 MHz clock cycle.

  • Bit 23 of the counter toggles about once every ~0.35 seconds.

  • LED = counter[23] means the LED will blink visibly.

Change to counter[22] for faster blink, counter[24] for slower.


Summary Table

StepToolPurpose
yosysSynthesizes Verilog to logic (JSON)
nextpnr-ice40Maps logic to real FPGA hardware
icepackConverts logic to bitstream
iceprogUploads the bitstream to iCEStick
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ampheo
ampheo