Backstory

This is my first ever blog, and honestly, I’m not quite sure how to start one.
But hey — here goes!

I’ve always loved computers, especially the magic behind how they work. As an Electronics student, I was introduced to subjects like Digital Electronics, Computer Organization, Computer-Aided Digital Design, Compilers, and Basic Computer Architecture — all of which fascinated me early on.

By my third semester, I thought I had found my core interests.
I was wrong.

Then came Digital Signal Processing, Control Systems, and Analog Circuit Design — and while I wasn’t exactly great at any of them, DSP hooked me. The moment I learned how the Fast Fourier Transform (FFT) could compute complex frequency data so efficiently, something clicked.

I’ve always been fascinated by the engineering mindset — how we take complex problems and solve them with efficiency and creativity. In DSP, that moment was the FFT: an optimization trick that reduces the computation of an \( N \) -point DFT from \( \mathcal{O}(N^2) \) to \( \mathcal{O}(N \log N) \) . That’s not just a math hack — it’s an engineering optimization that makes real-time audio and image processing possible on everyday hardware.

But this kind of clever design isn’t limited to DSP. It’s everywhere in digital design. Think about how multiplexers and encoders reduce datapath complexity, or how pipelining transforms a slow sequential system into a fast, overlapping one. These decisions — grounded in constraints, logic, and creativity — are what bring Integrated Circuits to life. From boolean algebra scribbled on a paper to billions of transistors on a 5nm chip, engineering optimization is something I try to understand, admire, and apply in nearly every project I build.

And to me, that’s real magic.

We literally enchanted a rock with electrons — and now it can stream videos, play games, simulate physics, and yes — even run my homemade instruction simulator :P

That idea — of blending Digital Logic, Computer Architecture, and Signal Processing — is what inspired me to create Resona. I was fascinated by how math, signal flow, and hardware design could come together in such elegant ways.

I’ll admit — I wasn’t a top scorer in DSP. But it made me think more deeply. Instead of solving textbook problems, I wanted to apply the concepts. That’s exactly what Resona v.1.0.0 became: a small, personal project that brings together everything I love — from packed SIMD instructions to low-level design — into a single experimental simulator.

Why I Built Resona v1.0.0

The original goal of Resona was to explore packed SIMD instructions under the RISC-V P extension. Having previously built both single-cycle and pipelined versions of RISC-V processors, I was already familiar with the RV32I ISA.

After studying the relevant instruction set from the RISC-V “P” Extension Proposal, I felt ready to take on the task. These packed instructions allow you to operate on multiple 8-bit or 16-bit values within a single 32-bit register — making them ideal for DSP-style workloads like dot products, convolutions, and transforms.

I wanted a simulation environment that was:

Minimal and easy to understand
Easy to extend with new instructions
Focused entirely on low-level behavior, not performance

So I wrote Resona in Rust and RISC-V Assembly, as a personal learning project — not just to simulate instructions, but to actually understand and debug them. Picking up Rust was no easy task, it has its own learning curve and that curve deserves respect. But luckily, I was equipped with great documentation and interactive resources — like the Brown University Rust Book, which includes quiz-style questions to reinforce learning. Rust for the Impatient is another great tutorial to understand the depth of the language.

What Can Resona v1.0.0 Do?

Resona is a Rust-RISC-V Assembly-based instruction simulator that currently supports:

RV32I base instructions
A small subset of the RISC-V P extension (e.g., KADD16, KSUB16, KSLRA16, PKBB16, SHFL) to explore packed 16-bit operations and instruction behavior.
Executable .bin file loading
Clean logging of each instruction and register state
Packed computation via custom assembly programs

Sample log output:

pc = 00000000 | instr = Add { rd: 1, rs1: 2, rs2: 3 } 
x1 = 0x10101010

You may wonder — “Oh wow, does it simulate CPU timing, caching, or pipelines like a real DSP processor?”
The answer is: No. Resona v1.0.0 focuses purely on correctness and clarity — it’s meant to be a clean testbed for understanding packed instruction behavior, not a full processor simulation.

What’s next for Resona v1.0.0?

DSP Kernels: Work in Progress

I would like to introduce the next step in building Resona v1.0.1 — running real DSP kernels, written manually in RISC-V assembly.

But what exactly is a DSP kernel? Sounds complicated, right?

In reality, a DSP kernel is just a small, highly optimized function that performs a core signal processing task — like a dot product, convolution, or an FFT. These kernels are often written in low-level languages (like assembly) to squeeze out every drop of performance, especially in systems where speed and efficiency matter most — like audio, video, and embedded applications.

For Resona, I managed to write the following kernels:

Dot Product
Discrete and Fast Fourier Transform (DFT, FFT)
Matrix Multiplication

These kernels are located in the test/kernels/ folder in the repo and are written in pure RISC-V assembly, ready to be executed within the Resona simulator.

The process of writing these kernels taught me a lot — from register allocation tricks to loop unrolling and instruction selection for performance. Even without results, writing these kernels deepened my understanding of packed SIMD operations and DSP design.

A snippet of pure FFT logic written in RISC-V Assembly.
This was one of those sessions where I nearly pulled my hair out, questioned all my choices, and considered breaking my desk — but somehow made it through.

My key learnings

Of course, Resona isn’t polished or production-ready — and that was never the goal. But I had a lot of fun building exactly what I wanted to, and I learned a ton along the way. Here are some of the key takeaways from the project:

Gained a deeper understanding of RISC-V instruction semantics
Practiced bit-level manipulation and low-level register logic
Wrote non-trivial RISC-V assembly kernels by hand (and survived!)

Overall Resona helped me bridge theory and practice in a way no textbook ever could. Really glad I took that DSP course after all :D

Future Enhancements for Resona and Final Thoughts

With Resona v1.0.0 now feature-complete — a single-cycle RV32I simulator written in Rust, supporting packed SIMD-style DSP instructions and hand-written assembly test programs — the next logical step is already underway:

Resona v2.0.0: Pipelined Execution

Resona v2.0.0 introduces a 5-stage pipelined CPU model: the plan is to lead this version with modular control logic, and early groundwork for performance-aware design.

This brings Resona a bit more closer to how real DSP processors behave — not in complexity or scale, but in concept. It's still intentionally minimal and educational.

If you’re curious about the pipeline design, branch plans, or upcoming milestones, you’ll find more details and updates on the repository’s GitHub Discussions.

Resona was never meant to be a perfect simulator. It began as an experiment — a personal learning project that merged my interests in digital logic, computer architecture, and signal processing. Along the way, I threw hands with toolchains, wrote untested kernels, misused Git, and spent a lot of time questioning my life choices while debugging FFT logic in assembly.

But that’s the fun of it.

I didn’t build Resona for performance or polish — I built it to understand. The experience has been more rewarding than any grade or assignment. If you’re someone who enjoys low-level design, bitwise chaos, or just learning by building cool things — I hope Resona inspires you to do the same.

BTS (Behind The Suffering Scenes)

Blood, sweat, and git reset --hard. No project goes smoothly, and Resona was no exception. Here are some fun bloopers I faced while building Resona.

.gitignore? Never heard of her.
At one point, I had over 60+ binary and log files accidentally staged in Git. I had forgot to setup .gitignore, and the next thing I knew my Git history looked like I was uploading a small OS image. Thankfully, I discovered Lazygit(thank you Rowjee)— the clean, beautiful Git TUI that saved me from doing sudo rm -rf --no-preserve-root. Easily one of the best tools I found during this project.

Toolchain pain
Building the RISC-V GCC toolchain with the P-extension enabled took hours. I’m not even sure what it was compiling — I’m convinced it silently tried to compile the entire distance between your home and Whitefield while pretending to build newlib.

I wish someone checked for my sanity also.

Resona v1.0.0: Rust, RISC-V Assembly, and DSP Kernels