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verilog

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27 followers·14 articles

verilog

#verilog·27 followers·14 articles

verilog

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Jayanth Mavilla

Jayanth Mavilla

world-of-electronics.hashnode.dev·Apr 08, 2025

Apr 08, 2025

🧠 Why I Started World of Electronics — and What You’ll Find Here

📌 The Problem As an M.Tech student specializing in VLSI Design, I realized something early:There’s no single place that teaches electronics for VLSI from the ground up, in a way that’s both practical and beginner-friendly. Most resources are either ...

🧠 Why I Started World of Electronics — and What You’ll Find Here

Discuss·13 reads

Shuran Xu

embeddedville.hashnode.dev·Feb 08, 2025

Feb 08, 2025

FPGA Prototyping in HLS C++ (Part 1)

Background Nowadays Field-Programmable Gate Arrays (FPGAs) have become a highly adaptable and powerful technology, allowing engineers to design custom, reconfigurable digital circuits. Their distinct blend of flexibility, parallel processing, and fas...

FPGA Prototyping in HLS C++ (Part 1)

Discuss·1 like·23 reads

Gursimran Singh

Gursimran Singh

blog.mixedsignal.tech·Jan 18, 2025

Jan 18, 2025

Digital Hardware Design : Finite State Machines

What is a Finite State Machine? FSMs are used to model systems that transit between a finite number of internal states. The transitions between different states depend on the current state and the external input. Hence FSMs are sequential circuits. P...

Digital Hardware Design : Finite State Machines

Digital System Design

Ayushi Lathiya

ayushilathiya.hashnode.dev·Dec 30, 2024

Dec 30, 2024

Building and Simulating a Binary Up-Down Counter Using Verilog/VHDL and Xilinx

Introduction Binary counters are an essential component in digital circuits, used in various applications such as timers, frequency dividers, and sequential logic designs. A Binary Up-Down Counter is a type of counter that can increment (count up) or...

Building and Simulating a Binary Up-Down Counter Using Verilog/VHDL and Xilinx

Discuss·1 like·33 reads

Bruce Röttgers

Bruce Röttgers

br-1683654367361.hashnode.dev·Mar 19, 2024

Mar 19, 2024

How to install Vivado on Ubuntu (or Ubuntu-based operating systems)

Download Installer Visit the official download page Click on the link to the Linux Self-Extracting Web Installer in the latest "Full Product Installation". (older versions do not work with Ubuntu 20.04 and later) You'll be prompted to create an ac...

Discuss·45 reads

Aazam Thakur

alcadeus.hashnode.dev·Feb 05, 2024

Feb 05, 2024

System Verilog: A student's guide

What is SystemVerilog? Imagine you're building a house. SystemVerilog is like the blueprints you use to plan everything. It's a special kind of language that people use to describe what electronic parts should be in a computer or any other device. It...

System Verilog: A student's guide

Discuss·1 like·10 reads

RISC-V Assembly

Md Ameenuddin Siddiqui

Md Ameenuddin Siddiqui

aisemi.hashnode.dev·Nov 20, 2023

Nov 20, 2023

Brain float

There is a trend in DL towards using FP16 instead of FP32 because lower precision calculations seem to be not critical for neural networks. Additional precision gives nothing, while being slower, takes more memory and reduces speed of communication. ...

Discuss·15 reads

VLSI circuit design

Shrihari

blog.xlogic.in·Aug 23, 2023

Aug 23, 2023

Makerchip Flows

Github: Click here This blog provides an overview of Makerchip Flows, which is a suite of EDA Flows created for taking TL-Verilog/Verilog designs through various ASIC/FPGA Design pathways and also provides a high-level picture of the frameworks devel...

Makerchip Flows

Discuss·359 reads

ABHISHEK ANAND

abhishekanand.hashnode.dev·Jun 15, 2023

Jun 15, 2023

GSoC 2023 (Week 1 and 2): Developing DSP48E1 primitive

Introduction The coding period for Google Summer of Code 2023 officially began on 29th May 2023. After almost a month of skimming through endless documentation, bonding with the community and connecting with fellow GSoC contributors, it's finally sho...

GSoC 2023 (Week 1 and 2): Developing DSP48E1 primitive

Discuss·14 likes·170 reads

ZhuoranWang

josephwang.hashnode.dev·Feb 12, 2023

Feb 12, 2023

HDLbits: My solution

HDLbits Getting started (1) Getting Started module top_module( output one ); // Insert your code here assign one = 1; endmodule (2) Zero module top_module( output zero );// Module body starts after semicolon endmodule Verilog language (1...

Discuss·533 reads

Shreyash Shukla

Shreyash Shukla

Noah Blake John

Noah Blake John

Viru singh

Wayne Bedford

Aakashi Jaiswal

Aakashi Jaiswal